1. Field
Example embodiments relate to semiconductor devices and/or methods of operating the same. For example, example embodiments are directed to a NAND flash memory device including 3-dimensionally arranged memory cell transistors and/or methods of operating the same.
2. Description of Related Art
Many electronic appliances include semiconductor devices including electronic elements, for example, transistors, resistors, and capacitors. The electronic elements are integrated on a semiconductor substrate after being designed to execute functions of the electronic appliances. For example, computers or digital cameras include semiconductor devices, for example, memory chips for storing data, processing chips for processing data, and so forth. The memory chips and the processing chips include electronic elements integrated on a semiconductor substrate.
A higher integration level for semiconductor devices is required to meet the higher performance and lower cost requirements of users. However, the development of advanced processing technologies is necessary to achieve a higher integration level for semiconductor devices. Increases in the integration level of semiconductor devices are limited because the development of advanced processing technologies incurs enormous expense and longer time.
In spite of the restrictions in advancing techniques for forming finer patterns, a reduction of the channel length of a cell transistor is limited by an issue of leakage current for semiconductor devices, e.g., flash memory devices. A cell current of a programmed cell transistor, during a read operation of the flash memory, should be lower than a desired, or alternatively, a predetermined reference current. However, the unintended leakage current of the cell transistor increases with a decrease in size of the cell transistor. The leakage current is a kind of short channel effect which appears if gate line width and channel length of the flash memory are reduced. The leakage current makes determining whether the cell transistor of the flash memory is programmed more difficult. Accordingly, a unit cell area of the flash memory (for example, channel length of the cell transistor) may not be further reduced without suppressing the leakage current of the cell transistor.
A conventional NAND flash memory device includes a string selection transistor, a ground selection transistor, and a plurality of cell transistors disposed therebetween. A conventional NAND flash memory device has a higher integration level among conventional existing semiconductor devices. With an increase in a number of cell transistors disposed between the two selection transistors, the area occupied by the selection transistors in an entire cell array region becomes smaller. Accordingly, the integration level of the flash memory may become higher with the decrease in the area occupied by the selection transistors.
However, conventional NAND flash memory devices suffer from not only the limitation resulting from leakage current but also from the limitation of a lower sensible current which interferes with an increase in integration level. If serially connected cell transistors continue to increase in number, electric resistance thereof increases during a read operation. Accordingly, read current at a desired, or alternatively, a predetermined cell becomes lower than a magnitude capable of being sensed by a sensing circuit. In this case, because the cell may not be normally read, the number of cell transistors disposed between the selection transistors is limited to 32 in most NAND flash memory devices. Therefore, the limitation of the lower sensible current makes reducing the area occupied by the selection transistors in the NAND flash memory more difficult.